Senior ASIC / FPGA Verification Engineer — California, United States

Senior ASIC / FPGA Verification Engineer

Location: Multiple locations across the United States

Contract Duration: 12 months

Working Arrangement: Hybrid working may be available, depending on location and project requirements.

The Opportunity

We are seeking experienced ASIC / FPGA Verification Engineers to join a leading engineering team working on complex digital hardware development.

You will take ownership of the verification of advanced digital subsystems across ASIC and FPGA platforms, managing the verification lifecycle from initial planning through to final sign-off.

This is an opportunity to contribute to verification strategy, develop robust UVM-based environments and help establish best practices across the wider engineering team.

We are interested in engineers at Senior and Principal level, with strong hands-on experience in SystemVerilog, UVM and complex digital verification.

Key Responsibilities

• Develop comprehensive verification and validation plans covering block, subsystem and system-level verification.

• Build and maintain UVM/SystemVerilog testbenches, including agents, monitors, drivers and scoreboards.

• Execute constrained-random and directed testing to verify complex digital designs.

• Drive functional and code coverage closure against defined verification objectives.

• Develop, review and implement assertions, supporting formal verification where appropriate.

• Maintain regression environments, investigate failures and work closely with RTL design teams to resolve issues.

• Analyse verification results against coverage targets and manage verification readiness through to sign-off.

• Support the development of verification methodologies, reusable environments and team standards.

• Mentor and provide technical guidance to junior verification engineers.

Required Experience & Skills

• Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering or a related discipline, or equivalent industry experience.

• 5–8+ years of experience in ASIC, SoC or FPGA verification engineering.

• Strong hands-on experience with SystemVerilog and UVM.

• Proven ability to develop verification environments and testbenches from scratch.

• Strong understanding of verification planning, functional coverage, code coverage and coverage closure.

• Experience with assertions and verification sign-off processes.

• Ability to work closely with RTL design teams throughout the development lifecycle.

Desirable Experience

Experience in one or more of the following areas would be advantageous:

• Formal property verification.

• Hardware emulation and performance validation.

• Low-power verification methodologies.

• Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) verification.

• DSP, communications or phased-array systems.

• High-Level Synthesis (HLS) verification.

• Safety-critical or high-reliability avionics engineering.

• Principal-level technical leadership and verification methodology development.

Candidate Eligibility Requirements

Due to project requirements, candidates must meet at least one of the following US eligibility criteria:

• US Citizen or US National.

• US Lawful Permanent Resident (Green Card holder).

• Individual admitted to the United States as a refugee.

• Individual granted asylum in the United States.